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Core1553BRT v4.0 Handbook
variable TX : std_logic;
variable GBR : std_logic;
begin
WC := CMDINT(4 downto 0);
BCAST := CMDINT(11);
GBR := INTVECT(6);
TX := INTVECT(5);
SA := INTVECT(4 downto 0);
MAPVECT <= GBR & BCAST & TX & SA & WC;
end process ;
end RTL;
Connecting the Backend to Internal FPGA Memory
When implementing the core in flash-based FPGA or Axcelerator devices, you can directly connect the
core to the flash-based FPGA or Axcelerator memory blocks. Use two memory blocks (1k×16 each—one
for transmit and the other for receive memory), as shown in Figure 7-3 .
RX
Memory
Read Write
BUSAINEN
BUSAINP
BUSAINN
TX
Memory
Write Read
BUSAOUTIN
BUSAOUTP
BUSAOUTN
BUSBINEN
BUSBINP
BUSBIN
BUSBOUTIN
BUSBOUTP
BUSBOUTN
Core1553BRT
Microsemi FPGA
Figure 7-3 ? Using Internal FPGA RAM Modules
The core must be in synchronous mode (ASYNCIF inactive—LOW). The MEMGNTn input should be tied
active (LOW) and the MEMWAITn input inactive (HIGH). This allows the backend to have immediate
access to the memory blocks.
Buffer Management
The core implements basic buffer management techniques for the 1553B message protocol. Receive
and transmit buffers are provided. This approach requires the backend system to empty and fill the
buffers promptly. For a “broadcast receive” command, the core generates an interrupt, indicating that a
receive buffer is available as the last data word is written to memory. At the same time, another receive
command to the same subaddress could be on the bus, which causes the first word in the memory to be
overwritten within 20 μs, depending on the backend request grant times. This time could be reduced to
less than 5 μs if the backend delays the core’s access to the memory for the last data word. It also allows
immediate access for the first data word in the following message.
Revision 3
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